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Am29SL160C
Data Sheet
The following document contains information on Spansion memory products. Although the document is marked with the name of the company that originally developed the specification, Spansion will continue to offer these products to existing customers.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 21635
Revision C
Amendment 5
Issue Date January 23, 2007
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29SL160C
16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES Secured Silicon (SecSi) Sector: 256-byte sector -- Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data -- Customer lockable: Customer may program own custom data. Once locked, data cannot be changed Zero Power Operation -- Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero Package options -- 48-ball FBGA -- 48-pin TSOP Top or bottom boot block Manufactured on 0.32 m process technology Compatible with JEDEC standards -- Pinout and software compatible with single-powersupply flash standard PERFORMANCE CHARACTERISTICS High performance -- Access time as fast 100 ns -- Program time: 8 s/word typical using Accelerate Ultra low power consumption (typical values) -- 1 mA active read current at 1 MHz -- 5 mA active read current at 5 MHz -- 1 A in standby or automatic sleep mode Minimum 1 million erase cycles guaranteed per sector 20 Year data retention at 125C -- Reliable operation for the life of the system SOFTWARE FEATURES Supports Common Flash Memory Interface (CFI) Erase Suspend/Erase Resume -- Suspends erase operations to allow programming in same bank Data# Polling and Toggle Bits -- Provides a software method of detecting the status of program or erase cycles Unlock Bypass Program command -- Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES Any combination of sectors can be erased Ready/Busy# output (RY/BY#) -- Hardware method for detecting program or erase cycle completion Hardware reset pin (RESET#) -- Hardware method of resetting the internal state machine to reading array data WP#/ACC input pin -- Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status -- Acceleration (ACC) function accelerates program timing Sector protection -- Hardware method of locking a sector, either insystem or using programming equipment, to prevent any program or erase operation within that sector -- Temporary Sector Unprotect allows changing data in protected sectors in-system
This Data Sheet states AMD's current specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21635 Rev: C Amendment/5 Issue Date: January 23, 2007
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GENERAL DESCRIPTION
The Am29SL160C is a 16 Mbit, 1.8 V volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The data appears on DQ0-DQ15. The device is offered in 48-pin TSOP and 48-ball FBGA packages. The word-wide data (x16) appears on DQ15-DQ0; the byte-wide (x8) data appears on DQ7-DQ0. This device is designed to be programmed and erased in-system with a single 1.8 volt VCC supply. No VPP is required for program or erase operations. The device can also be programmed in standard EPROM programmers. The standard device offers access times of 90, 100, 120, or 150 ns, allowing microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 1.8 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm--an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle completes, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This is achieved in-system or via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses are stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes. AMD's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
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TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 Special Handling Instructions for FBGA Packages .................. 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29SL160C Device Bus Operations ...............................9
Write Operation Status . . . . . . . . . . . . . . . . . . . . 27 DQ7: Data# Polling ................................................................. 27
Figure 5. Data# Polling Algorithm .................................................. 27
RY/BY#: Ready/Busy# ............................................................ 28 DQ6: Toggle Bit I .................................................................... 28 DQ2: Toggle Bit II ................................................................... 28 Reading Toggle Bits DQ6/DQ2 ............................................... 28 DQ5: Exceeded Timing Limits ................................................ 29 DQ3: Sector Erase Timer ....................................................... 29
Figure 6. Toggle Bit Algorithm........................................................ 29 Table 13. Write Operation Status ................................................... 30
Word/Byte Configuration .......................................................... 9 Requirements for Reading Array Data ..................................... 9 Writing Commands/Command Sequences ............................ 10 Accelerated Program Operation ............................................. 10 Program and Erase Operation Status .................................... 10 Standby Mode ........................................................................ 10 Automatic Sleep Mode ........................................................... 10 RESET#: Hardware Reset Pin ............................................... 10 Output Disable Mode .............................................................. 11
Table 2. Am29SL160CT Top Boot Sector Architecture ..................12 Table 3. Am29SL160CB Bottom Boot Sector Architecture .............13
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 31
Figure 7. Maximum Negative Overshoot Waveform ...................... 31 Figure 8. Maximum Positive Overshoot Waveform........................ 31
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 31 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) .............................................................................. 33 Figure 10. Typical ICC1 vs. Frequency ............................................ 33
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 11. Test Setup..................................................................... 34 Table 14. Test Specifications ......................................................... 34 Figure 12. Input Waveforms and Measurement Levels ................. 34
Autoselect Mode ..................................................................... 14
Table 4. Am29SL160C Autoselect Codes (High Voltage Method) ..14
Sector/Sector Block Protection and Unprotection .................. 15
Table 5. Top Boot Sector/Sector Block Addresses for Protection/Unprotection .............................................................15 Table 6. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection ...........................................15
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35 Read Operations .................................................................... 35
Figure 13. Read Operations Timings ............................................. 35
Hardware Reset (RESET#) .................................................... 36
Figure 14. RESET# Timings .......................................................... 36
Write Protect (WP#) ................................................................ 16 Temporary Sector Unprotect .................................................. 16
Figure 1. In-System Sector Protect/Unprotect Algorithms .............. 17 Figure 2. Temporary Sector Unprotect Operation........................... 18
Word/Byte Configuration (BYTE#) ........................................ 37
Figure 15. BYTE# Timings for Read Operations............................ 37 Figure 16. BYTE# Timings for Write Operations............................ 37
Secured Silicon (SecSi) Sector Flash Memory Region .......... 18
Table 7. SecSi Sector Addresses ...................................................18
Erase/Program Operations ..................................................... 38
Figure 17. Program Operation Timings.......................................... Figure 18. Chip/Sector Erase Operation Timings .......................... Figure 19. Data# Polling Timings (During Embedded Algorithms). Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... Figure 21. DQ2 vs. DQ6................................................................. Figure 22. Temporary Sector Unprotect Timing Diagram .............. Figure 23. Accelerated Program Timing Diagram.......................... Figure 24. Sector Protect/Unprotect Timing Diagram .................... Figure 25. Alternate CE# Controlled Write Operation Timings ...... 39 40 41 41 42 42 43 43 45
Hardware Data Protection ...................................................... 18 Common Flash Memory Interface (CFI) . . . . . . . 19
Table 8. CFI Query Identification String ..........................................19 Table 9. System Interface String .....................................................20 Table 10. Device Geometry Definition ............................................20 Table 11. Primary Vendor-Specific Extended Query ......................21
Command Definitions . . . . . . . . . . . . . . . . . . . . . 21 Reading Array Data ................................................................ 21 Reset Command ..................................................................... 21 Autoselect Command Sequence ............................................ 22 Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 22 Word/Byte Program Command Sequence ............................. 22
Figure 3. Program Operation .......................................................... 23
Chip Erase Command Sequence ........................................... 24 Sector Erase Command Sequence ........................................ 24 Erase Suspend/Erase Resume Commands ........................... 24
Figure 4. Erase Operation............................................................... 25
Erase And Programming Performance . . . . . . . 46 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 46 TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 46 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . 47 TS 048--48-Pin Standard TSOP ............................................ 47 FBC048--48-Ball Fine-Pitch Ball Grid Array (FBGA) 8 x 9 mm package .................................................................. 48 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 49
Command Definitions ............................................................. 26
Table 12. Am29SL160C Command Definitions ..............................26
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PRODUCT SELECTOR GUIDE
Family Part Number Speed Options Max access time, ns (tACC) Max CE# access time, ns (tCE) Max OE# access time, ns (tOE) Note:See "AC Characteristics" for full specifications. -100 100 100 35 Am29SL160C -120 120 120 50 -150 150 150 65
BLOCK DIAGRAM
RY/BY#
VCC VSS Sector Switches Erase Voltage Generator Input/Output Buffers DQ0-DQ15 (A-1)
RESET#
WE# BYTE# WP#/ACC
State Control Command Register
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0-A19
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CONNECTION DIAGRAMS
A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# RESET# NC WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Standard TSOP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
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CONNECTION DIAGRAMS (Continued)
48-Ball FBGA (Top View, Balls Facing Down)
A6 A13 A5 A9 A4 WE# A3
B6 A12 B5 A8 B4 RESET# B3
C6 A14 C5 A10 C4 NC C3 A18 C2 A6 C1 A2
D6 A15 D5 A11 D4 A19 D3 NC D2 A5 D1 A1
E6 A16 E5 DQ7 E4 DQ5 E3 DQ2 E2 DQ0 E1 A0
F6
G6
H6 VSS H5 DQ6 H4 DQ4 H3 DQ3 H2 DQ1 H1 VSS
BYTE# DQ15/A-1 F5 DQ14 F4 DQ12 F3 DQ10 F2 DQ8 F1 CE# G5 DQ13 G4 VCC G3 DQ11 G2 DQ9 G1 OE#
RY/BY# WP#/ACC A2 A7 A1 A3 B2 A17 B1 A4
Special Handling Instructions for FBGA Packages
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time.
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PIN CONFIGURATION
A0-A19 = 20 addresses DQ0-DQ14 = 15 data inputs/outputs DQ15/A-1 CE# OE# WE# = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) = Chip enable = Output enable = Write enable
LOGIC SYMBOL
20 A0-A19 DQ0-DQ15 (A-1) CE# OE# WE# WP#/ACC RESET# BYTE# RY/BY# 16 or 8
WP#/ACC = Hardware write protect/acceleration pin RESET# BYTE# RY/BY# VCC VSS NC = Hardware reset pin, active low = Selects 8-bit or 16-bit mode = Ready/Busy# output = 1.8-2.2 V single power supply = Device ground = Pin not connected internally
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ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.
Am29SL160C T -100 E C N
STANDARD PROCESSING
N = SecSi Sector factory-locked with random ESN (Contact an AMD representative for more information)
TEMPERATURE RANGE
C= I= D= F=
Commercial (0C to +70C) Industrial (-40C to +85C) Commercial (0oC to +70oC) with Pb-free Package Industrial (-40oC to +85oC) with Pb-free Package
PACKAGE TYPE
E
=
WC =
48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) 48-ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 8 x 9 mm package (FBC048)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top sector B = Bottom sector
DEVICE NUMBER/DESCRIPTION
Am29SL160C 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS Flash Memory 1.8 Volt-only Read, Program, and Erase
Valid Combinations for TSOP Packages AM29SL160CT-100, AM29SL160CB-100 AM29SL160CT-120, AM29SL160CB-120 AM29SL160CT-150, AM29SL160CB-150 EC, EI ED, EF
Valid Combinations for FBGA Packages Order Number AM29SL160CT-100, AM29SL160CB-100 AM29SL160CT-120, AM29SL160CB-120 AM29SL160CT-150, AM29SL160CB-150 Package Marking A160CT10V, A160CB10V A160CT12V, A160CB12V A160CT15V, A160CB15V C, I, D, F
WCC, WCI, WCD, WCF
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
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DEVICE BUS OPERATIONS
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.
Table 1.
Am29SL160C Device Bus Operations
DQ8-DQ15 Addresses (Note 1) AIN AIN X X X Sector Address, A6 = L, A1 = H, A0 = L Sector Address, A6 = H, A1 = H, A0 = L AIN DQ0- DQ7 DOUT DIN High-Z High-Z High-Z DIN BYTE# = VIH DOUT DIN High-Z High-Z High-Z X BYTE# = VIL DQ8-DQ14 = High-Z, DQ15 = A-1 High-Z High-Z High-Z X
Operation Read Write (Program/Erase) Standby Output Disable Reset Sector Protect (Note 2) Sector Unprotect (Note 2) Temporary Sector Unprotect
CE# L L VCC 0.2 V L X L
OE# WE# RESET# WP#/ACC L H X H X H H L X H X L H H VCC 0.2 V H L VID X (Note 3) X X X X
L X
H X
L X
VID VID
(Note 3) (Note 3)
DIN DIN
X DIN
X High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 10 1.0 V, VHH = 10 0.5 V, X = Don't Care, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL). 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See "Sector/Sector Block Protection and Unprotection" on page 15. 3. If WP#/ACC = VIL, the two outermost boot sectors are protected. If WP#/ACC = VIH, the two outermost boot sectors are protected or unprotected as previously set by the system. If WP#/ACC = VHH, all sectors, including the two outermost boot sectors, are unprotected.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15-DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic `1', the device is in word configuration, DQ15-DQ0 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic `0', the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at V IH . The BYTE# pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array 9
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DATA data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Reading Array Data" on page 21 for more information. Refer to the AC table for timing specifications and to Figure 13, on page 35 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data.
SHEET If the system asserts VHH on the pin, the device automatically enters the aforementioned Unlock Bypass mode and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation.
Program and Erase Operation Status
During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7-DQ0. Standard read cycle timings and ICC read specifications apply. Refer to "Write Operation Status" on page 27 for more information, and to "AC Characteristics" on page 35 for timing diagrams.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to "Word/Byte Configuration" on page 9 for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The "Word/Byte Program Command Sequence" on page 22 contains details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 2, on page 12 and Table 3, on page 13 indicate the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. The "Command Definitions" on page 21 contains details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7-DQ0. Standard read cycle timings apply in this mode. Refer to "Autoselect Mode" on page 14 and "Autoselect Command Sequence" on page 22 for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" on page 35 contains timing specification tables and timing diagrams for write operations.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC 0.2 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC 0.2 V, the device is in the standby mode, but the standby current is greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. The device also enters the standby mode when the RESET# pin is driven low. Refer to "RESET#: Hardware Reset Pin" on page 10. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 50 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification.
Accelerated Program Operation
The device offers accelerated program operation through the ACC function, which is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster in-system programming of the device during the system production process. 10
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the 21635C5 January 23, 2007
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DATA RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/ write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS 0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS 0.2 V, the standby current is greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
SHEET If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data t RH after the RESET# pin returns to VIH. Refer to "AC Characteristics" on page 35 for RESET# parameters and to "RESET# Timings" on page 36 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.
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DATA Table 2.
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Am29SL160CT Top Boot Sector Architecture
Address Range (in Hexadecimal Byte Mode (x8) 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1F1FFFh 1F2000h-1F3FFFh 1F4000h-1F5FFFh 1F6000h-1F7FFFh 1F8000h-1F9FFFh 1FA000h-1FBFFFh 1FC000h-1DFFFFh 1FE000h-1FFFFFh Word Mode (x16) 00000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh 40000h-47FFFh 48000h-4FFFFh 50000h-57FFFh 58000h-5FFFFh 60000h-67FFFh 68000h-6FFFFh 70000h-77FFFh 78000h-7FFFFh 80000h-87FFFh 88000h-8FFFFh 90000h-97FFFh 98000h-9FFFFh A0000h-A7FFFh A8000h-AFFFFh B0000h-B7FFFh B8000h-BFFFFh C0000h-C7FFFh C8000h-CFFFFh D0000h-D7FFFh D8000h-DFFFFh E0000h-E7FFFh E8000h-EFFFFh F0000h-F7FFFh F8000h-F8FFFh F9000h-F9FFFh FA000h-FAFFFh FB000h-FBFFFh FC0004-FCFFFh FD000h-FDFFFh FE000h-FEFFFh FF000h-FFFFFh
Sector Address Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 A19 A18 A17 A16 A15 A14 A13 A12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1
Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4
Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See "Word/Byte Configuration" section for more information.
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DATA
SHEET
Table 3. Am29SL160CB Bottom Boot Sector Architecture
Sector Address Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A17 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A14 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Sector Size (Kbytes/Kwords) 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Address Range (in hexadecimal) Byte Mode (x8) 000000h-001FFFh 002000h-003FFFh 004000h-005FFFh 006000h-07FFFFh 008000h-009FFFh 00A000h-00BFFFh 00C000h-00DFFFh 00E000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh Word Mode (x16) 00000h-00FFFh 01000h-01FFFh 02000h-02FFFh 03000h-03FFFh 04000h-04FFFh 05000h-05FFFh 06000h-06FFFh 07000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh 40000h-47FFFh 48000h-4FFFFh 50000h-57FFFh 58000h-5FFFFh 60000h-67FFFh 68000h-6FFFFh 70000h-77FFFh 78000h-7FFFFh 80000h-87FFFh 88000h-8FFFFh 90000h-97FFFh 98000h-9FFFFh A0000h-A7FFFh A8000h-AFFFFh B0000h-B7FFFh B8000h-BFFFFh C0000h-C7FFFh C8000h-CFFFFh D0000h-D7FFFh D8000h-DFFFFh E0000h-E7FFFh E8000h-EFFFFh F0000h-F7FFFh F8000h-FFFFFh
Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See "Word/Byte Configuration" section for more information.
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DATA
SHEET must appear on the appropriate highest order address bits (see Tables 2 and 3). Table 4 shows the remaining address bits that are don't care. When all necessary bits are set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 12, on page 26. This method does not require VID. See "Command Definitions" on page 21 for details on using the autoselect mode.
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 4. In addition, when verifying sector protection, the sector address
Table 4.
Am29SL160C Autoselect Codes (High Voltage Method)
A19 A11 to to WE# A12 A10 H H X X H H X X H VID X L X L H X X E7 01h (protected) 00h (unprotected) 81h (factory locked) VID X L X L H X 22h E4 E7 X X A8 to A7 X A5 to A2 X DQ8 to DQ15 X 22h DQ7 to DQ0 01h E4
Description
Mode
CE# L L L L L
OE# L L L L L
A9 VID
A6 L
A1 L
A0 L
Manufacturer ID: AMD Device ID: Am29SL160CT (Top Boot Block) Device ID: Am29SL160CB (Bottom Boot Block) Word Byte Word Byte
Sector Protection Verification
L
L
H
SA
X
VID
X
L
X
H
L X
SecSi Sector Indicator bit (DQ7)
L
L
H
SA
X
VID
X
L
X
H
H
X
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care. Note: Outputs for data bits DQ8-DQ15 are for BYTE#=VIH. DQ8-DQ15 are don't care when BYTE#=VIL.
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SHEET Table 6. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection
Sector / Sector Block SA38 SA37-SA35 SA34-SA31 SA30-SA27 SA26-SA23 SA22-SA19 SA18-SA15 SA14-SA11 A19-A12 11111XXX 11110XXX, 11101XXX, 11100XXX 110XXXXX 101XXXXX 100XXXXX 011XXXXX 010XXXXX 001XXXXX 00001XXX, 00010XXX, 00011XXX 00000111 00000110 00000101 00000100 00000011 00000010 00000001 00000000 Sector / Sector Block Size 64 Kbytes 192 (3x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 192 (3x64) Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes
Sector/Sector Block Protection and Unprotection
(Note: For the following discussion, the term "sector" applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table 5 and Table 6). Table 5. Top Boot Sector/Sector Block Addresses for Protection/Unprotection
A19-A12 00000XXX 00001XXX, 00010XXX, 00011XXX 001XXXXX 010XXXXX 011XXXXX 100XXXXX 101XXXXX 110XXXXX 11100XXX, 11101XXX, 11110XXX 11111000 11111001 11111010 11111011 11111100 11111101 11111110 11111111 Sector / Sector Block Size 64 Kbytes 192 (3x64) Kbytes
Sector / Sector Block SA0 SA1-SA3 SA4-SA7 SA8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
SA10-SA8 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 192 (3x64) Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection is implemented via two methods.
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DATA The primary method requires VID on the RESET# pin only, and is implemented either in-system or via programming equipment. Figure 1, on page 17 shows the algorithms and Figure 24, on page 43 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only AMD flash devices. Publication number 21622 contains further details. Contact an AMD representative to request the document containing further details. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD's ExpressFlashTM Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See "Autoselect Mode" on page 14 for details.
SHEET using the method described in "Sector/Sector Block Protection and Unprotection" on page 15. The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device. If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the two outermost 8 Kbyte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotection" on page 15. Note that if the system asserts VHH on the WP#/ACC pin, all sectors, including the two outermost sectors, are unprotected. VHH is intended for accelerated insystem programming of the device during system production. It is advisable, therefore, not to assert VHH on this pin after the system has been placed in the field for use. If faster programming is desired, the system may use the unlock bypass program command sequence.
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 2, on page 18 shows the algorithm, and Figure 22, on page 42 shows the timing diagrams, for this feature.
Write Protect (WP#)
The write protect function provides a hardware method of protecting certain boot sectors without using VID. This function is one of two provided by the WP#/ACC pin. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two "outermost" 8 Kbyte boot sectors independently of whether those sectors were protected or unprotected
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START PLSCNT = 1 RESET# = VID Wait 1 s Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address
START PLSCNT = 1 RESET# = VID Wait 1 s
Temporary Sector Unprotect Mode
No
First Write Cycle = 60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Wait 150 s Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Read from sector address with A6 = 0, A1 = 1, A0 = 0 No
No First Write Cycle = 60h? Yes All sectors protected? Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0
Temporary Sector Unprotect Mode
Increment PLSCNT
Reset PLSCNT = 1
Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0
No No PLSCNT = 25? Yes Data = 01h?
Increment PLSCNT
Yes
No Yes No
Read from sector address with A6 = 1, A1 = 1, A0 = 0 Set up next sector address
Device failed
Protect another sector? No Remove VID from RESET#
PLSCNT = 1000? Yes
Data = 00h? Yes
Device failed Write reset command
Last sector verified? Yes
No
Sector Protect Algorithm
Sector Protect complete
Sector Unprotect Algorithm
Remove VID from RESET#
Write reset command Sector Unprotect complete
Figure 1.
In-System Sector Protect/Unprotect Algorithms
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DATA
SHEET on page 22). Table 7, on page 18 shows the layout for the SecSi Sector.
START Table 7. RESET# = VID (Note 1) Perform Erase or Program Operations RESET# = VIH SecSi Sector Addresses
Address Range Description 16-byte random ESN User-defined code or factory erased (all 1s) Word Mode (x16) Byte Mode (x8) 00-07h 08-7Fh 000-00Fh 010-0FFh
Temporary Sector Unprotect Completed (Note 2)
Notes: 1. All protected sectors unprotected. (If WP#/ACC = VIL, the outermost sectors remain protected) 2. All previously protected sectors are protected once again.
The device continues to read from the SecSi Sector until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 12, on page 26 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during V CC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than V LKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up.
Figure 2.
Temporary Sector Unprotect Operation
Secured Silicon (SecSi) Sector Flash Memory Region
The Secured Silicon (SecSi) Sector is a flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector in this device is 256 bytes in length. The device contains a SecSi Sector indicator bit that allows the system to determine whether or not the SecSi Sector was factory locked. This indicator bit is permanently set at the factory and cannot be changed, which prevents a factory-locked part from being cloned. AMD offers this device only with the SecSi Sector factory serialized and locked. The first sixteen bytes of the SecSi Sector contain a random ESN. To utilize the remainder SecSi Sector space, customers must provide their code to AMD through AMD's Express Flash service. The factory will program and permanently protect the SecSi Sector (in addition to programming and protecting the remainder of the device as required). The system can read the SecSi Sector by writing the Enter SecSi Sector command sequence (see "Enter SecSi Sector/Exit SecSi Sector Command Sequence"
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SHEET given in Table 8, on page 19 to Table 11, on page 21. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Table 8, on page 19 to Table 11, on page 21. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/products/nvd/overv i ew / c f i . h t m l . A l t e r n a t i ve l y, c o n t a c t a n A M D representative for copies of these documents.
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses
Table 8.
Addresses (Word Mode) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Addresses (Byte Mode) 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h
CFI Query Identification String
Description Query Unique ASCII string "QRY"
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
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DATA Table 9.
Addresses (Word Mode) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Addresses (Byte Mode) 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch Data 0018h 0022h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h
SHEET
System Interface String
Description VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 10.
Addresses (Word Mode) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Addresses (Byte Mode) 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h Data 0015h 0002h 0000h 0000h 0000h 0002h 0007h 0000h 0020h 0000h 001Eh 0000h 0000h 0001h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
Device Geometry Definition
Description Device Size = 2 byte Flash Device Interface description (refer to CFI publication 100) Max. number of bytes in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100)
N
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
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DATA Table 11.
Addresses (Word Mode) 40h 41h 42h 43h 44h 45h 46h 47h 48h Addresses (Byte Mode) 80h 82h 84h 86h 88h 8Ah 8Ch 8Eh 90h
SHEET
Primary Vendor-Specific Extended Query
Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock 0 = Required, 1 = Not Required Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 01 = 29F040 mode, 02 = 29F016 mode, 03 = 29F400 mode, 04 = 29LV800A mode Simultaneous Operation 00 = Not Supported, 01 = Supported Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
Data 0050h 0052h 0049h 0031h 0030h 0000h 0002h 0001h 0001h
49h
92h
0004h
4Ah 4Bh 4Ch
94h 96h 98h
0000h 0000h 0000h
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. Table 12, on page 26 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in "AC Characteristics" on page 35.
Erase Suspend mode, the system may once again read array data with the same exception. See "Erase Suspend/Erase Resume Commands" on page 24 for more information on this mode. The system must issue the reset command to reenable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See "Reset Command", next. See also "Requirements for Reading Array Data" on page 9 for more information. The table provides the read parameters, and Figure 13, on page 35 shows the timing diagram.
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence 21
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DATA before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies dur ing Erase Suspend). See "AC Characteristics" on page 35 for parameters, and to Figure 14, on page 36 for the timing diagram.
SHEET Flash Memor y Region" on page 18 for fur ther information.
Word/Byte Program Command Sequence
The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 12, on page 26 shows the address and data r e q u i r e m e n t s fo r t h e byt e p r o gra m c o m m a n d sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See "Write Operation Status" on page 27 for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Byte Program command sequence should be reinitiated once the device resets to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the operation and set DQ5 to "1", or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read shows that the data is still "0". Only erase operations can convert a "0" to a "1". Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A twocycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programm i n g t i m e . Ta bl e 1 2 , o n p a g e 2 6 s h o w s t h e requirements for the command sequence.
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 12, on page 26 shows the address and data requirements. This method is an alternative to that shown in Table 4, on page 14, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address 01h in word mode (or 02h in byte mode) returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Table 2, on page 12 and Table 3, on page 13 for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data.
Enter SecSi Sector/Exit SecSi Sector Command Sequence
The SecSi Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi command sequence. The Exit SecSi command sequence returns the device to normal operation. Table 12, on page 26 shows the address and data requirements for both command sequences. See also "Secured Silicon (SecSi) Sector 22
Am29SL160C
21635C5 January 23, 2007
DATA During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don't cares. The device then returns to reading array data. The device offers accelerated program operations through the WP#/ACC pin. This function is intended only to speed in-system programming of the device during system production. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH for any operation other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 3 illustrates the algorithm for the program operation. See "Erase/Program Operations" on page 38 for parameters, and Figure 17, on page 39 for timing diagrams.
SHEET
START
Write Program Command Sequence
Embedded Program algorithm in progress
Data Poll from System
Verify Data?
No
Yes No
Increment Address
Last Address?
Yes Programming Completed
Note: See Table 12, on page 26 for program command sequence.
Figure 3.
Program Operation
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DATA
SHEET be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts are re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See "DQ3: Sector Erase Timer" on page 29.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation begins, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device returns to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to "Write Operation Status" on page 27 for information on these status bits.) Figure 4, on page 25 illustrates the algorithm for the erase operation. Refer to the "Erase/Program Operations" on page 38 for parameters, and to Figure 18, on page 40 for timing diagrams.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 12, on page 26 shows the address and data requirements for the chip erase command sequence. Any commands wr itten to the chip dur ing the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device returns to reading array data, to ensure data integrity. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See "Write Operation Status" on page 27 for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 4, on page 25 illustrates the algorithm for the erase operation. See "Erase/Program Operations" on page 38 for parameters, and Figure 18, on page 40 for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table 12, on page 26 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise the last address and command might not 24
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are "don't-cares" when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation.
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DATA After the erase operation is suspended, the system can read array data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See "Write Operation Status" on page 27 for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation Status" on page 27 for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See "Autoselect Command Sequence" on page 22 for more information. The system must write the Erase Resume command (address bits are "don't care") to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another
SHEET Erase Suspend command can be written after the device resumes erasing.
START
Write Erase Command Sequence
Data Poll from System
Embedded Erase algorithm in progress
No
Data = FFH?
Yes Erasure Completed
Notes: 1. See Table 12, on page 26 for erase command sequence. 2. See "DQ3: Sector Erase Timer" on page 29 for more information.
Figure 4.
Erase Operation
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DATA
SHEET
Command Definitions
Table 12.
Command Sequence (Note 1)
Read (Note 6) Reset (Note 7) Manufacturer ID Autoselect (Note 8) Device ID (Top Boot/Bottom Boot) SecSi Sector Factory Protect Sector Protect Verify (Note 9) Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte 4 4 3 4 4
Am29SL160C Command Definitions
Second Addr Data Bus Cycles (Notes 2-5) Third Fourth Addr Data Addr Data Fifth Addr Data Sixth Addr Data
Cycles
1 1 4
First Addr Data
RA XXX 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA XXX BA 555 AAA 555 AAA BA BA 55 AA AA AA AA AA AA AA A0 90 AA AA B0 30 98 RD F0 AA
2AA 555 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555 PA XXX 2AA 555 2AA 555
55
555 AAA 555 AAA
90
X00 X01 X02
01 22E4/ 22E7 E4/E7
4
AA
55
90
55 55 55 55 55 55 PD 00 55 55
555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA
90 90 88 90 A0 20
X03 X06 (SA)X02 (SA)X04
Enter SecSi Sector Region Exit SecSi Sector Region Program Unlock Bypass
XXX PA
00 PD
3 2 2
6 6 1 1
Unlock Bypass Program (Note 10) Unlock Bypass Reset (Note 11) Chip Erase Sector Erase Erase Suspend (Note 12) Erase Resume (Note 13) CFI Query (Note 14) Legend: X = Don't care Word Byte Word Byte Word Byte
555 AAA 555 AAA
80 80
555 AAA 555 AAA
AA AA
2AA 555 2AA 555
55 55
555 AAA SA
10 30
1
RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. Notes: 1. See Table 1, on page 9 for description of bus operations. 2. 3. 4. 5. 6. 7. All values are in hexadecimal. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. Data bits DQ15-DQ8 are don't cares in byte mode. Unless otherwise noted, address bits A19-A11 are don't cares. No unlock or command cycles required when in read mode. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when in the autoselect mode, or if DQ5 goes high (while providing status information). The fourth cycle of the autoselect command sequence is a read cycle.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19-A12 uniquely select any sector.
9.
The data is 00h for an unprotected sector and 01h for a protected sector. Data bits DQ15-DQ8 are don't care. See the Autoselect Command Sequence section for more information.
10. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 11. The Unlock Bypass Reset command is required to return to the read mode when in the unlock bypass mode. 12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 13. The Erase Resume command is valid only during the Erase Suspend mode. 14. Command is valid when device is ready to read array data or when device is in autoselect mode.
8.
26
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DATA
SHEET
WRITE OPERATION STATUS
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 13, on page 30 and the following subsections describe the functions of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an embedded program or erase operation is in progress or is completed. page 41, Data# Polling Timings (During Embedded Algorithms), in the "AC Characteristics" section illustrates this. Table 13, on page 30 shows the outputs for Data# Polling on DQ7. Figure 5, on page 27 shows the Data# Polling algorithm.
START
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 s, then the device returns to reading array data. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to "1"; prior to this, the device outputs the "complement," or "0." The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects DQ7 changes from the complement to true data, it can read valid data at DQ7- DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (OE#) is asserted low. Figure 19, on
Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No No
DQ5 = 1?
Yes Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No FAIL PASS
Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5.
Figure 5.
Data# Polling Algorithm
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DATA
SHEET DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 13, on page 30 shows the outputs for Toggle Bit I on DQ6. Figure 6, on page 29 shows the toggle bit algorithm. Figure 20, on page 41 shows the toggle bit timing diagrams. Figure 21, on page 42 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on "DQ2: Toggle Bit II".
RY/BY#: Ready/Busy#
RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 13, on page 30 shows the outputs for RY/BY#. Figure 14, on page 36, Figure 17, on page 39 and Figure 18, on page 40 shows RY/BY# for reset, program, and erase operations, respectively.
DQ2: Toggle Bit II
The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. The device toggles DQ2 with each OE# or CE# read cycle. DQ2 toggles when the system reads at addresses within those sectors that were selected for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 13, on page 30 to compare outputs for DQ2 and DQ6. Figure 6, on page 29 shows the toggle bit algorithm in flowchart form, and the section "DQ2: Toggle Bit II" explains the algorithm. See also the "DQ6: Toggle Bit I" subsection. Figure 20, on page 41 shows the toggle bit timing diagram. Figure 21, on page 42 shows the differences between DQ2 and DQ6 in graphical form.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle (The system may use either OE# or CE# to control the read cycles). When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on "DQ7: Data# Polling" on page 27). If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6, on page 29 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device successfully completed the program or erase operation. If it is still toggling, the 21635C5 January 23, 2007
28
Am29SL160C
DATA device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 is not high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6).
SHEET to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 13, on page 30 shows the outputs for DQ3.
START
Read DQ7-DQ0
(Note 1)
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a "1" to a location that is previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the operation exceeds the timing limits, DQ5 produces a "1." Under both these conditions, the system must issue the reset command to return the device to reading array data.
No Read DQ7-DQ0
Toggle Bit = Toggle? Yes
No
DQ5 = 1?
Yes
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation began. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from "0" to "1." If the time between additional sector erase commands from the system are assumed to be less than 50 s, the system need not monitor DQ3. See also the "Sector Erase Command Sequence" on page 24. After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device accepted the command sequence, and then read DQ3. If DQ3 is "1", the internally controlled erase cycle started; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0", the device accepts additional sector erase commands. To ensure the command is accepted, the system software should check the status of DQ3 prior
Read DQ7-DQ0 Twice
(Notes 1, 2)
Toggle Bit = Toggle?
No
Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete
Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to "1". See text.
Figure 6.
Toggle Bit Algorithm
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DATA Table 13.
Operation Standard Mode Erase Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspend-Program
SHEET
Write Operation Status
DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 1) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 2) No toggle Toggle Toggle Data N/A RY/BY# 0 0 1 1 0
DQ7 (Note 2) DQ7# 0 1 Data DQ7#
Notes: 1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation exceeds the maximum timing limits. See "DQ5: Exceeded Timing Limits" on page 29 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
30
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DATA
SHEET
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -65C to +125C Voltage with Respect to Ground VCC (Note 1). . . . . . . . . . . . . . . . . -0.5 V to +2.5 V A9, OE#, and RESET# (Note 2) . . . . . . . . -0.5 V to +11.0 V All other pins (Note 1) . . . . . -0.5 V to VCC + 0.5 V Output Short Circuit Current (Note 3) . . . . . . 100 mA
Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8. 2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is -0.5 V. During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC input voltage on pin A9 is +11.0 V which may overshoot to +12.5 V for periods up to 20 ns. Maximum DC input voltage on pin WP#/ACC is +10.0 V which may overshoot to +11.5 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns 20 ns 0.0 V -0.5 V -2.0 V 20 ns 20 ns
Figure 7. Maximum Negative Overshoot Waveform
20 ns
Figure 8. Maximum Positive Overshoot Waveform
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . . . 0C to +70C Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . -40C to +85C VCC Supply Voltages VCC, all speed options . . . . . . . . . . . .+1.8 V to +2.2 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
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DATA
SHEET
DC CHARACTERISTICS CMOS Compatible
Parameter ILI ILIT ILO Description Input Load Current A9 Input Load Current Output Leakage Current Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max; A9 = 11.0 V VOUT = VSS to VCC, VCC = VCC max CE# = VIL, OE# = VIH, Byte Mode CE# = VIL, OE# = VIH, Word Mode CE# = VIL, OE# = VIH CE#, RESET# = VCC0.2 V RESET# = VSS 0.2 V VIH = VCC 0.2 V; VIL = VSS 0.2 V -0.5 0.8 x VCC 8.5 5 MHz 1 MHz 5 MHz 1 MHz 5 1 5 1 20 1 1 1 Min Typ Max 1.0 35 1.0 10 3 mA 10 3 30 5 5 5 0.2 x VCC VCC + 0.3 9.5 mA A A A V V V Unit A A A
ICC1
VCC Active Read Current (Notes 1, 2)
ICC2 ICC3 ICC4 ICC5 VIL VIH VHH
VCC Active Write Current (Notes 2, 3, 5) VCC Standby Current (Note 2) VCC Reset Current (Note 2) Automatic Sleep Mode (Notes 2, 3) Input Low Voltage Input High Voltage Voltage for WP#/ACC Sector Protect/Unprotect and Program Acceleration Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage (Note 4)
VID VOL VOH VLKO
VCC = 2.0 V IOL = 100 A, VCC = VCC min IOH = -100 A, VCC = VCC min
9.0
11.0 0.1
V
VCC-0.1 1.2 1.5 V
Notes: 1. The ICC current listed is typically less than 1 mA/MHz, with OE# at VIL. Typical VCC is 2.0 V. 2. The maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 50 ns. 5. Not 100% tested.
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DC CHARACTERISTICS (Continued) Zero Power Flash
20 Supply Current in mA
15
10
5
0 0 500 1000 1500 2000 Time in ns
Note: Addresses are switching at 1 MHz
2500
3000
3500
4000
Figure 9.
ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
10
8 Supply Current in mA 2.2 V 6
4 1.8 V 2
0 1 2 3 Frequency in MHz
Note: T = 25 C
4
5
Figure 10.
Typical ICC1 vs. Frequency
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TEST CONDITIONS
Table 14.
Test Condition Device Under Test CL Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 30 5 0.0-2.0 1.0 1.0
Test Specifications
-100 -120, -150 1 TTL gate 100 pF ns V V V Unit
Figure 11.
Test Setup
Key To Switching Waveforms
WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS
2.0 V 0.0 V
Input
1.0 V
Measurement Level
1.0 V
Output
Figure 12.
Input Waveforms and Measurement Levels
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AC CHARACTERISTICS Read Operations
Parameter JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ Std tRC tACC tCE tOE tDF tDF Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Read tOEH Output Enable Hold Time (Note 1) Toggle and Data# Polling CE# = VIL OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Min Min Min Speed Option -100 100 100 100 35 -120 120 120 120 50 16 16 0 30 0 -150 150 150 150 65 Unit ns ns ns ns ns ns ns ns ns
tAXQX
tOH
Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1)
Notes: 1. Not 100% tested. 2. See Figure 11, on page 34 and Table 14, on page 34 for test specifications.
.
tRC Addresses CE# tOE tOEH WE# HIGH Z Outputs RESET# RY/BY# Output Valid tCE tOH HIGH Z tDF Addresses Stable tACC
OE#
0V
Figure 13.
Read Operations Timings
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DATA
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AC CHARACTERISTICS Hardware Reset (RESET#)
Parameter JEDEC Std tREADY tREADY tRP tRH tRB Description RESET# Pin Low (During Embedded Algorithms) to Read or Write (see Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (see Note) RESET# Pulse Width RESET# High Time Before Read (see Note) RY/BY# Recovery Time Test Setup Max Max Min Min Min All Speed Options 20 500 500 200 0 Unit s ns ns ns ns
Note: Not 100% tested.
RY/BY#
CE#, OE# tRH RESET# tRP tReady
Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
tReady RY/BY# tRB CE#, OE#
RESET# tRP
Figure 14.
RESET# Timings
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AC CHARACTERISTICS Word/Byte Configuration (BYTE#)
Parameter JEDEC Std tELFL/tELFH tFLQZ tFHQV Description CE# to BYTE# Switching Low or High BYTE# Switching Low to Output HIGH Z BYTE# Switching High to Output Active Max Max Min 50 100 -100 Speed Options -120 10 60 120 60 150 -150 Unit ns ns ns
CE#
OE#
BYTE# tELFL DQ0-DQ14
BYTE# Switching from word to byte mode
Data Output (DQ0-DQ14)
Data Output (DQ0-DQ7) Address Input
DQ15/A-1
DQ15 Output tFLQZ tELFH
BYTE# BYTE# Switching from byte to word mode
DQ0-DQ14
Data Output (DQ0-DQ7) Address Input tFHQV
Data Output (DQ0-DQ14) DQ15 Output
DQ15/A-1
Figure 15.
BYTE# Timings for Read Operations
CE# The falling edge of the last WE# signal WE#
BYTE#
tSET (tAS)
tHOLD (tAH)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 16.
BYTE# Timings for Write Operations
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AC CHARACTERISTICS Erase/Program Operations
Parameter JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tELWL tWHEH tWLWH tWHWL Std. tWC tAS tAH tDS tDH tGHWL tCS tCH tWP tWPH Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Byte Programming Operation (Notes 1, 2) tWHWH1 tWHWH1 Word Accelerated Program Operation, Byte or Word (Note 2) tWHWH2 tWHWH2 tVCS tRB tBUSY Notes: 1. Not 100% tested. 2. See "Erase And Programming Performance" on page 46 for more information. Sector Erase Operation (Notes 1, 2) VCC Setup Time Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay Typ Typ Typ Min Min Max 12 8 2 50 0 200 s sec s ns ns Min Min Min Min Min Min Min Min Min Min Typ 50 50 50 -100 100 Speed Options -120 120 0 60 60 0 0 0 0 60 30 10 s 70 70 70 -150 150 Unit ns ns ns ns ns ns ns ns ns ns
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AC CHARACTERISTICS
Program Command Sequence (last two cycles) tAS tWC Addresses 555h PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# tVCS VCC Status DOUT tRB tWPH tWHWH1 Read Status Data (last two cycles)
PA
PA
tCH
A0h
Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode.
Figure 17.
Program Operation Timings
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AC CHARACTERISTICS
Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA
555h for chip erase
Read Status Data
VA tAH
VA
CE#
OE# tWP WE# tCS tDS
tCH
tWPH
tWHWH2
tDH Data 55h 30h
10 for Chip Erase In Progress Complete
tBUSY RY/BY# tVCS VCC
tRB
Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status"). 2. Illustration shows device in word mode.
Figure 18.
Chip/Sector Erase Operation Timings
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AC CHARACTERISTICS
tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7
High Z
VA
VA
tOE tDF
Complement
Complement
True
Valid Data
High Z
DQ0-DQ6 tBUSY RY/BY#
Status Data
Status Data
True
Valid Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 19.
Data# Polling Timings (During Embedded Algorithms)
tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ6/DQ2 tBUSY RY/BY#
High Z
VA
VA
VA
tOE tDF
Valid Status (first read)
Valid Status (second read)
Valid Status (stops toggling)
Valid Data
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 20.
Toggle Bit Timings (During Embedded Algorithms)
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AC CHARACTERISTICS
Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2 Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.
Figure 21. DQ2 vs. DQ6
Temporary Sector Unprotect
Parameter JEDEC Std tVIDR tVHH tRSP Description VID Rise and Fall Time VHH Rise and Fall Time RESET# Setup Time for Temporary Sector Unprotect Min Min Min All Speed Options 500 500 4 Unit ns ns s
VID RESET# 0 or 1.8 V tVIDR Program or Erase Command Sequence CE# tVIDR 0 or 1.8 V
WE# tRSP RY/BY#
Figure 22. Temporary Sector Unprotect Timing Diagram
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AC CHARACTERISTICS
VHH WP#/ACC VIL or VIH tVHH tVHH VIL or VIH
Figure 23.
Accelerated Program Timing Diagram
VID VIH
RESET#
SA, A6, A1, A0
Valid* Sector Protect/Unprotect
Valid* Verify 40h
Sector Protect: 150 s Sector Unprotect: 15 ms
Valid*
Data 1 s CE#
60h
60h
Status
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 24.
Sector Protect/Unprotect Timing Diagram
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AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations
Parameter JEDEC tAVAV tAVEL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL Std. tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Programming Operation (Notes 1, 2) tWHWH1 tWHWH1 Byte Word Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Typ 50 50 50 Speed Options -100 100 -120 120 0 60 60 0 0 0 0 60 30 10 s 12 8 2 s sec 70 70 70 -150 150 Unit ns ns ns ns ns ns ns ns ns ns
Accelerated Program Operation, Byte or Word (Note 2) tWHWH2 tWHWH2 Sector Erase Operation (Notes 1, 2)
Notes: 1. Not 100% tested. 2. See "Erase And Programming Performance" on page 46 for more information.
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AC CHARACTERISTICS
555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase
Data# Polling PA
Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH
A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase
tAS tAH
tWHWH1 or 2
tBUSY
DQ7#
DOUT
RESET#
RY/BY#
Notes: 1. PA = program address, PD = program data, DQ7# = complement of the data written, DOUT = data written 2. Figure indicates the last two bus cycles of command sequence. 3. Word mode address used as an example.
Figure 25.
Alternate CE# Controlled Write Operation Timings
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ERASE AND PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Accelerated Program Time, Word/Byte Chip Programming Time (Note 3) Byte Mode Word Mode Typ (Note 1) 2 70 10 12 8 20 14 300 360 240 160 120 Max (Note 2) 15 Unit s s s s s s s Excludes system level overhead (Note 5) Comments Excludes 00h programming prior to erasure (Note 4)
Notes: 1. Typical program and erase times assume the following conditions: 25C, 2.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 1.8 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 12, on page 26 for further information on command definitions. 6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Includes all pins except VCC. Test conditions: VCC = 1.8 V, one pin at a time. Min -1.0 V -0.5 V -100 mA Max 11.0 V VCC + 0.5 V +100 mA
TSOP PIN CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
DATA RETENTION
Parameter Minimum Pattern Data Retention Time 125C 20 Years Test Conditions 150C Min 10 Unit Years
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PHYSICAL DIMENSIONS* TS 048--48-Pin Standard TSOP
Dwg rev AA; 10/99
* For reference only. BSC is an ANSI standard for Basic Space Centering.
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PHYSICAL DIMENSIONS FBC048--48-Ball Fine-Pitch Ball Grid Array (FBGA) 8 x 9 mm package
Dwg rev AF; 10/99
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REVISION SUMMARY Revision A (December 1998)
Initial release.
Revision A+5 (July 23, 1999)
Global Added 90 ns speed option.
Revision A+1 (January 1999)
Distinctive Characteristics WP#/ACC pin: In the third subbullet, deleted reference to increased erase performance. Device Bus Operations Accelerated Program and Erase Operations: Deleted all references to accelerated erase. Sector/Sector Block Protection and Unprotection: Changed section name and text to include tables and references to sector block protection and unprotection. AC Characteristics Accelerated Program Timing Diagram: Deleted reference in title to accelerated erase.
Revision A+6 (September 1, 1999)
AC Characteristics Hardware Reset (RESET#) table: Deleted tRPD specification. Erase/Program Operations table: Deleted tOES specification.
Revision A+7 (September 7, 1999)
Distinctive Characteristics Ultra low power consumption bullet: Corrected values to match those in the DC Characteristics table. AC Characteristics Alternate CE# Controlled Erase/Program Operations: Deleted tOES specification.
Revision A+2 (March 23, 1999)
Connection Diagrams Corrected the TSOP pinout on pins 13 and 14.
Revision B (December 14, 1999)
AC Characteristics--Figure 17. Program Operations Timing and Figure 18. Chip/Sector Erase Operations Deleted tGHWL and changed OE# waveform to start at high. Physical Dimensions Replaced figures with more detailed illustrations.
Revision A+3 (April 12, 1999)
Global Modified the description of accelerated programming to emphasize that it is intended only to speed in-system programming of the device during the system production process. Distinctive Characteristics Secured Silicon (SecSi) Sector bullet: Added the 8-byte unique serial number to description. Device Bus Operations table Modified Note 3 to indicate sector protection behavior when VIH is asserted on WP#/ACC. Applied Note 3 to the WP#/ACC column for write operations. Ordering Information Added the "N" designator to the optional processing section. Secured Silicon (SecSi) Sector Flash Memory Region Modified explanatory text to indicate that devices now have an 8-byte unique ESN in addition to the 16-byte ra n d om E S N . A d d e d t able fo r a d d re s s ra ng e clarification.
Revision C (February 21, 2000)
Removed "Advance Information" designation from data sheet. Data sheet parameters are now stable; only speed, package, and temperature range combinations are expected to change in future revisions. Device Bus Operations table Changed standby voltage specification to VCC 0.2 V. Standby Mode Changed standby voltage specification to VCC 0.2 V. DC Characteristics table Changed test conditions for ICC3, ICC4, ICC5 to VCC 0.2 V.
Revision C+1 (November 14, 2000)
Global Added dash to speed options and OPNs. Added table of contents. AC Characteristics--Read Operations Changed tDF to 16 ns for all speeds.
Revision A+4 (May 14, 1999)
Global Deleted all references to the unique ESN.
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DATA
SHEET Valid Combinations for FBGA Packages Added WCD, and WCF to Order Number column, and added D, and F to Package Marking column.
Revision C+2 (June 11, 2002)
Secured Silicon (SecSi) Sector Flash Memory Region Deleted reference to A-1 not being used in addressing, and to address bits that are don't cares. In Table 7, changed lower address bit for user-defined code to 08h (word mode) and 010h (byte mode).
Revision C4 (July 13, 2005)
Global Deleted 90 ns speed option. Ordering Information Deleted options for extended temperature range in Pbfree packages.
Revision C+3 (November 1, 2004)
Global Added colophon and reference links. Ordering Information Added temperature ranges for Pb-free Package Valid Combinations for TSOP Packages Added ED, and EF combinations.
Revision C5 (January 23, 2007)
Erase and Program Operations table Changed tBUSY to a maximum specification.
Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks Copyright (c)1998-2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Copyright (c) 2006-2007 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.
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